Monday 19
16:00 – 18:30
| P1 | Near field scanning microwave microscope using a coaxial cavity resonator for the characterization of semiconductor structures
B. Abadlia Bagdad, F.Gamiz Departamento de Electrónica y Tecnología de Computadores, Universidad de Granada, 18071 Granada, Spain |
| P2 | Energy Harvesting Power Management Circuit Design in 22nm FDSOI Technology
Z. E. Kaya, S. B. Tekin, S. Kalem Informatics & Information Security Research Center TUBITAK-BILGEM, Gebze, Kocaeli, Turkey |
| P3 | Ferroelectric FET as a Low Power Device with reduced SCE and RDF Effect
Ullas Pandey1, Koushik Guha1, K.L.Baishnab1,Brinda Bhowmick1 and Madhumita Paul1 1Dept. of ECE, National Institute of Technology, Silchar, Assam, 788010, India |
| P4 | Indium oxide nanostructures for RRAM integration in CMOS-BEOL
A. Souifi1, E. A. León Pérez1, P.-V. Guenery1, K. Ayadi1, S. Brottet1, N. Baboux1, L. Militaru1, J. Moeyaert2, S. Labau2, T. Baron2, and S. Blonkowski3 1Univ. Lyon, Institut des Nanotechnologies de Lyon UMR CNRS 5270, INSA Lyon, Villeurbanne, France. 2Univ. Grenoble Alpes, Laboratoire des Technologies de la Microélectronique, UMR CNRS 5129, Grenoble, France. 3STMicroelectronics, 850 Rue Jean Monnet, 38920 Crolles, France |
| P5 | Investigation of Memory Effect with Voltage or Current Charging Pulse Bias in MIS Structures based on codoped Si-NCs
Andrzej Mazurak, Jakub Jasiński, Robert Mroczyński Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa 75, 00-662 Warsaw, Poland |
| P6 | Reliability of Z2-FET
Sehyun Kwon1,5, Navarro Carlos2, Francisco Gamiz2, Philippe Galy3, Asen Asenov4, Sorin Cristoloveanu5, Jinho Ahn6, and Yong Tae Kim1 1Semiconductor Materials and Device Lab, Korea Institute of Science and Technology, Seoul 02792, Korea 2Nanoelectronics Research Group, University of Granada, 18071 Granada, Spain 3STMicroelectronics, 38920 Crolles, France, Grenoble, France 4University of Glasgow, Glasgow G128QQ, U.K 5IMEP-LaHC, Minatec, Grenoble INP, Univ. Grenoble Alpes, CNRS, 38016 Grenoble, France 6Division of Materials Science and Engineering, Hanyang University, Seoul 04763, Korea |
| P7 | Electrical Characterization of HfO2 Based Resistive RAM Devices Having Different Bottom Electrode Metallizations
S. B. Tekin1, S. Kalem1, Z. E. Kaya1, E. Jalaguier2 1Informatics & Information Security Research Center TUBITAK-BILGEM, Gebze, Kocaeli, Turkey 2CEA-LETI, 17 Avenue des Martyrs, 38054, Grenoble, France |
| P8 | Design of Dickson Rectifier for RF Energy Harvesting in 28 nm FD-SOI technology
M. Awad, P. Benech and J-M Duchamp The University Grenoble Alpes, CNRS, Grenoble INP, IMEP-LAHC, 38000 Grenoble, France |
| P9 | A Low Noise Wideband VCO with 4 bit Switched Capacitor Array
K.L. Baishnab1, K. Guha1, S. Chanda1, N.M Laskar1, Madhumita Paul1 1National Institute of Technology, Silchar, Assam. 788010. India |
| P10 | FoMPy: A figure of merit extraction tool for semiconductor device simulations
Gabriel Espiñeira, Natalia Seoane, Daniel Nagy, Guillermo Indalecio, Antonio J. García Loureiro Centro Singular de Investigación en Tecnoloxías da Información, Univ. of Santiago de Compostela, Spain |
| P11 | Impact of TFET Reverse Currents Into Circuit Operation: A Case Study
Juan Núñez Instituto de Microelectrónica de Sevilla, IMSE-CNM (CSIC/Uni. de Sevilla) Av. Américo Vespucio s/n, 41092, Sevilla (Spain). |
| P12 | Nanoindentation effects on the electrical caracterization in Ψ-MOSFET configuration
Licinius Benea1, Maryline Bawedin1, Cécile Delacour2, Sorin Cristoloveanu1, Irina Ionica1 1IMEP-LaHC, Minatec, Grenoble INP, Univ. Grenoble Alpes, CNRS, 38016 Grenoble, France 2Néel Inst., CNRS, 38042 Grenoble, France |
| P13 | Impact of Electron Effective Mass Variation on the Performance of InAs/GaSb Electron-Hole Bilayer Tunneling Field-Effect Transistor
J. L. Padilla1, C. Medina-Bailón2, M. Rupakula3, C. Alper3, C. Sampedro1, F. Gámiz1 and A. M. Ionescu3 1Departamento de Electrónica, Universidad de Granada, Granada, Spain. ES-18071 2Device Modelling Group, University of Glasgow, Glasgow, UK, G12 8QQ 3Nanoelectronic Devices Laboratory, École Polytechnique Fédérale de Lausanne, Lausanne, Switzerland, CH-1015 |
| P14 | Hole mobility of cylindrical GaSb nanowires
Francisco G. Ruiz1, Enrique G. Marín2, Celso Martínez-Blanque1, I. M. Tienda-Luna1, J. M. Gonzalez-Medina1, A. Toral1, L. Donetti1, A. Godoy1 1Dpto. Electrónica y Tec. Computadores, Fac. de Ciencias, Univ. Granada, Fuentenueva S/N, 18071 Granada, Spain 2Dipto. di Ingegneria dell Informazione, Università di Pisa, Via G. Caruso 16, 56122 Pisa, Italy. |
| P15 | New method for self-heating estimation using only DC measurements
C. A. B. Mori1, P. G. D. Agopian1,2, J. A. Martino1 1LSI/PSI/USP, University of Sao Paulo, Sao Paulo, Brazil 2Sao Paulo State University (UNESP), Sao Joao da Boa Vista, Brazil |
| P16 | Profiling Border-Traps by TCAD analysis of Multifrequency CV-curves in Al2O3/InGaAs stacks
E. Caruso1, J. Lin1 K. F. Burke1, K. Cherkaoui1, D. Esseni2, F. Gity1, S. Monaghan1, P. Palestri2, P. Hurley1, L. Selmi3 1Tyndall National Institute University College Cork, Cork, Ireland 2DPIA, University of Udine, Via delle Scienze 206, 33100, Udine, Italy 3DIEF, University of Modena and Reggio Emilia, Via P. Vivarelli 10/1, 41125, Modena, Italy |
| P17 | MS-EMC vs. NEGF: A Comparative Study Accounting for Transport Quantum Corrections
C. Medina-Bailon1, C. Sampedro1, J.L. Padilla1, A. Godoy1, L. Donetti1, F. Gamiz1 and A. Asenov2 1Departamento de Electrónica y Tecnología de Computadores, Universidad de Granada, 18071 Granada, Spain 2School of Engineering, University of Glasgow, Glasgow G12 8LT, Scotland, UK |
| P18 | Switching Current Reduction in Advanced Spin-Orbit Torque MRAM
Viktor Sverdlov, Alexander Makarov, and Siegfried Selberherr Institute for Microelectronics, TU Wien, Gußhausstraße 27-29, 1040 Vienna, Austria |
| P19 | Finite Element Simulation of 2D Percolating Silicon-Nanonet Field-Effect Transistor
T.Cazimajou, M.Mouis, G.Ghibaudo Univ. Grenoble Alpes, CNRS, Grenoble INP, IMEP-LAHC, 38016 Grenoble, France |
| P20 | Investigation on built-in BJT in FD-SOI BIMOS
T. Bedecarrats1,2,3, P. Galy1, S. Cristoloveanu2, C. Fenouillet-Beranger3 1STMicroelectronics, 850 rue jean Monnet, 38926 Crolles Cedex, France 2Univ. Grenoble Alpes, IMEP-LAHC, Grenoble INP Minatec, CNRS, F-38000 Grenoble, France 3CEA, LETI, Minatec Campus, and Univ. Grenoble Alpes, 38054 Grenoble, France |
| P21 | Simulation and Automated Characterisation of Optimal Load for Flexible Composite Generators Based on Piezoelectric ZnO Nanowires
D. Menin1,2, M. Parmar1, R. Tao1, P. Oliveira1, M. Mouis1, L. Selmi3 and G. Ardila1 1Univ. Grenoble Alpes, CNRS, Grenoble INP, IMEP-LaHC, F-38000 Grenoble, France 2Università degli Studi di Udine, DPIA, Udine, Italy 3IUNET Consortium and DIEF, Università di Modena e Reggio Emilia, Italy |
| P22 | Unified Feature Scale Model for Etching in SF6 and Cl Plasma Chemistries
Xaver Klemenschits, Siegfried Selberherr, and Lado Filipovic Institute for Microelectronics, TU Wien, Gußhausstraße 27-29/E360, 1040 Vienna, Austria |
| P23 | A Design-oriented Charge-based Simplified Model for FDSOI MOSFETs
Alessandro Pezzotta1, Farzan Jazaeri1, Heorhii Bohuslavskyi2, Louis Hutin2, Christian Enz1 1ICLAB, École Polytechnique Fédérale de Lausanne (EPFL), Neuchâtel, Switzerland 2CEA Leti, Grenoble, France |
| P24 | Characterization of gate overlap capacitances and effective channel size in MOSFETs
Daniel Tomaszewski, Grzegorz Głuszko, Jolanta Malesińska Institute of Electron Technology (ITE), Al. Lotników 32/46, 02-668 Warsaw, Poland |
| P25 | Effect of Schottky Barrier Contacts on Measured Capacitances in Tunnel-FETs
A. Farokhnejad1,2, M. Schwarz1, M. Graef1, F. Horst1,2, B. Iñíguez2, F. Lime2 and A. Kloes1 1NanoP, TH Mittelhessen University of Applied Sciences, Giessen, Germany 2DEEEA, Universitat Rovira i Virgili, Tarragona, Spain |
| P26 | An Efficient Model for Charge and Gate Capacitance in III-V Cylindrical Nanowire Transistors
Mohit D. Ganeriwala1, Enrique G. Marin2, Francisco G. Ruiz3 and Nihar R. Mohapatra1 1Department of Electrical Engineering, Indian Institute of Technology, Gandhinagar, India 2Department of Information Engineering, University of Pisa, Italy 3Department of Electronics, University of Granada, Spain |
| P27 | Design Benefits of Self-Cascode Configuration for Analog Applications in 28nm FDSOI Technology
Lígia Martins d’Oliveira1, Michelly de Souza1, Valeriya Kilchytska2, Denis Flandre2 1Centro Universitário FEI, São Bernardo do Campo, Brazil 2ICTEAM, Université catholique de Louvain, Louvain la-Neuve, Belgium. |
| P28 | Impact of BOX thickness and Ground-Plane on non-linearity of UTBB FD-SOI MOS Transistors
Mandar S. Bhoir and Nihar R. Mohapatra Department of Electrical Engineering, Indian Institute of Technology Gandhinagar (IIT GN), Gujarat, India |
| P29 | Multilevel Parallelization Approach to Estimate Spin Lifetime in Silicon: Performance Analysis
J. Ghosh1, D. Osintsev2, V. Sverdlov2, and S. Ganguly1 1Department of Electrical Engineering, Indian Institute of Technology, Mumbai, India 2Institute for Microelectronics, TU Wien, Gußhausstraße 27–29/E360, A–1040 Wien, Austria |
| P30 | Realization of Vertical Ge nanowires for Gate-All-Around transistors
M. Liu1, K. Mertens1, S. Glass1, S. Trellenkamp2, S. Mantl1, D. Buca1, Q.T. Zhao1 1Peter-Grünberg-Institut (PGI 9) and JARA-Fundamentals of Future Information Technologies, Forschungszentrum Jülich, Germany 1Helmholtz Nano Facility (HNF), Germany |
| P31 | Scaling down a level shifter circuit in 28 nm FDSOI Technology
Saikat Chatterjee, Ulrich Rückert Cognitronics and Sensor Systems Group CITEC, Bielefeld University 33619, Germany |
| P32 | Effects of Post Metallization Annealing on InGaAs-on-Insulator MOSFETs on Si
Cezar B. Zota, Clarissa Convertino, Daniele Caimi, Marilyne Sousa and Lukas Czornomaz IBM Research GmbH Zürich Laboratory, Säumerstrasse 4, CH-8803 Rüschlikon, Switzerland |
| P33 | Linear Distortion Analysis of 3D Double Gate Junctionless Transistor with High-k Dielectrics
A. Baidya1, S. Baishya2 and T. R. Lenka2 1Department of Electronics and Communication Engineering, Mizoram University, Aizawl, India, 796004 2Department of Electronics and Communication Engineering, National Institute of Technology Silchar, Assam, India, 788010 |
| P34 | InSb Nanocrystals Containing SOI Structures: Preparation and Properties
I.E. Tyschenko, V.A. Volodin, A.G. Cherkov, and V.P. Popov A.V. Rzhanov Institute of Semiconductor Physics, Novosibirsk, Russia |
| P35 | Detailed analysis of frequency-dependent impedance in pseudo-MOSFET on thin SOI film
S. Sato1,2, G. Ghibaudo2, L. Benea2, Y. Omura1 and S. Cristoloveanu2 1Faculty of Engineering Science, Kansai University, Osaka, Japan 2IMEP-LAHC, Grenoble Institute of Technology, Minatec, Grenoble, France |
| P36 | Potential of Thin (~10 nm) HfO2 Ferroelectric FDSOI NCFET for Performance Enhancement in Digital Circuits at Reduced Power Consumption
S. Qureshi and Shruti Mehrotra Department of Electrical Engineering, Indian Institute of Technology Kanpur-208016, India |
| P37 | Three P-Silicon Layers in Reliable Lateral Double Diffused Metal Oxide Semiconductor Transistor
Mahsa Mehrad School of Engineering, Damghan University, Damghan, Iran |
| P38 | Inserting PN Junction in a Power Device for Achieving Improved Figure Of Merit
Meysam Zareiee, Hesam Salami School of Engineering, Damghan University, Damghan |
| P39 | Design of Wideband Cascode Low Noise Amplifier using E-mode GaN based MOSHEMT for RF and Microwave Applications
D. K. Panda, and T. R. Lenka Microelectronics and VLSI Design Group, Department of Electronics and Communication Engineering, National Institute of Technology Silchar, Assam, 788010, India |
| P40 | Analytical Model Development for Gate Workfunction Engineered Short Channel E-mode n-Polar GaN MOS-HEMT
D. K. Panda, and T. R. Lenka Microelectronics and VLSI Design Group, Department of Electronics and Communication Engineering, National Institute of Technology Silchar, Assam, 788010, India |