SESSION 2

Memories I

Monday 19

12:00 – 12:20 Simulation Study on Z2FET Scalability, Process Optimization and Their Impact on Performance

M. Duan1, F. Adamu-Lema1, C. Navarro2, F. Gamiz2, A. Asenov1

1University of Glasgow, Rankine Building, Oakfield Ave., Glasgow, G12 8LT, UK

2University of Granada, Spain

12:20 – 12:40 Z2-FET Memory Matrix in 28 nm Technology

Mukta Singh Parihar1, Kyung Hwa Lee1, Hyung Jin Park1, Carlos Navarro3, Joris Lacord2, Francisco Gamiz3, Maryline Bawedin1 and Sorin Cristoloveanu1

1Univ. Grenoble Alpes, IMEP-LAHC, Grenoble INP Minatec, CNRS, F-38000 Grenoble, France

2CEA-LETI, Minatec Campus, 38054 Grenoble, France

3Univ. of Granada, Spain

12:40 – 13:00 Evaluation of thin-oxide Z2-FET DRAM cell

 1S. Navarro, 2K. H. Lee, 1C. Marquez, 1C. Navarro, 2M. Parihar, 2M. Bawedin, 2H. Park, 3P. Galy, 1F. Gamiz and 2S. Cristoloveanu

1Nanoelectronics Research Group, University of Granada, 18071, Granada (Spain)

2IMEP-LAHC, Minatec Campus, 38000, Grenoble (France)

3STMicroelectronics, 38920, Crolles (France)