Poster session
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P1 |
1D Drift-Diffusion transport in 2D-material based FETs with vertical contacts A. Toral-Lopez, E.G. Marin, F. Pasadas, M.C. Pardo, J. Cuesta, F.G. Ruiz and A. Godoy PEARL Laboratory, Dpto. de Electrónica y Tecnología de Computadores, Universidad de Granada (Spain) |
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P2 |
A generalizable, uncertainty-aware neural network potential for GeSbTe with Monte Carlo dropout Sung-Ho Lee1, Valerio Olevano2, Benoît Sklénard1,3 1Univ. Grenoble Alpes, CEA, Leti (France) 2Université Grenoble Alpes (France) 3CNRS, Institut Néel (France) |
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P3 |
A Machine-learning-based Multi-Objective Optimization of Stacked Nanosheet Transistors for sub-3nm technology node Haoqing Xu1,2, Weizhuo Gan1,2, Lei Cao1,2, Huaxiang Yin1,2 and Zhenhua Wu1,2 1Institute of Microelectronics, Chinese Academy of Sciences (China) 2School of Integrated Circuits, University of Chinese Academy of Sciences (China) |
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P4 |
Ab Initio Quantum Transport Simulations of Monolayer GeS Nanoribbons Mislav Matić and Mirko Poljak Computational Nanoelectronics Group, Faculty of Electrical Engineering and Computing, University of Zagreb (Croatia) |
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P5 |
Acceleration of Semiconductor Device Simulation Using Compact Charge Model Kwang-Woon Lee and Sung-Min Hong School of Electrical Engineering and Computer Science, Gwangju Institute of Science and Technology (Republic of Korea) |
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P6 |
Atomic-scale study of silane and hydrogen adsorptions competition during Si epitaxy Laureline Treps, Jing Li and Benoît Sklénard Univ. Grenoble Alpes, CEA, Leti (France) |
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P7 |
Automatic Grid Refinement for Thin Material Layer Etching in Process TCAD Simulations Christoph Lenz1, Paul Manstetten2, Andreas Hössinger3 and Josef Weinbub1 1Christian Doppler Laboratory for High Performance TCAD at the 2Institute for Microelectronics, TU Wien (Austria) 3Silvaco Europe Ltd. (United Kingdom) |
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P8 |
Comparative Analysis of NBTI Modeling Frameworks – BAT and Comphy Aseer Israr Ansari, Nilotpal Choudhury, Narendra Parihar and Souvik Mahapatra Department of Electrical Engineering, Indian Institute of Technology Bombay (India) |
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P9 |
Disorders in delta-layer tunnel junctions Juan P. Mendez and Denis Mamaluy Sandia National Laboratories (USA) |
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P10 |
Ferroelectric FDSOI FET Modeling for Memory and Logic Applications Swetaki Chatterjee1, Shubham Kumar2, Amol Gaidhane3, Chetan Kumar Dabhi4, Yogesh S. Chauhan2, Hussam Amrouch1 1Chair of Semiconductor Test and Reliability, University of Stuttgart (Germany) 2Indian Institute of Technology (India) 3Arizona State University (USA) 4University of California (USA) |
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P11 |
Hierarchical Simulation of Nanosheet Field Effect Transistor: NESS Flow D. Nagy1,2, A. Rezaei1, N. Xeni1, T. Dutta1, F. Adamu-Lema1,2, I. Topaloglu1, V. P. Georgiev1 and A. Asenov1,2 1Device Modelling Group, School of Engineering, University of Glasgow (Scotland, UK) 2Semiwise Ltd. (Scotland, UK) |
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P12 |
Improvement of On-cell Metrology Using Spectral Imaging with TCAD Modeling Byungseong Ahn1, Kwangseok Lee1, Jaehun Yang1, Jiseong Doh1, Jaehoon Jeong1, Minseok Kim2, Yeonjeong Kim2, Jongchul Kim2, Hyung Keun Yoo2, Dae Sin Kim1 1Computational Science and Engineering Team 2Foundry Metrology & Inspection Team / Device Solution Business, Samsung Electronics Co., Ltd. (Republic of Korea) |
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P13 |
Modeling Optical Second Harmonic Generation for Oxide Semiconductor Interface Characterization Binit Mallick1, Dipankar Saha1, Anindya Dutta2 and Swaroop Ganguly1 1Department of Electrical Engineering, Indian Institute of Technology (India) 2Department of Chemistry, Indian Institute of Technology (India) |
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P14 |
Modeling Thermal Effects in STT-MRAM Tomáš Hadámek1, Wolfgang Goes2, Siegfried Selberherr3 and Viktor Sverdlov3 1Christian Doppler Laboratory for Nonvolatile Magnetoresistive Memory and Logic at the 3Institute for Microelectronics, TU Wien (Austria) 2Silvaco Europe Ltd. (United Kingdom) |
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P15 |
Monolithic TCAD Simulation of Phase-Change (PCM/PRAM) + Ovonic Threshold Switch (OTS) Selector Device M. Thesberg1, Z. Stanojevic1, O. Baumgartner1, C. Kernstock1, D. Leonelli2, M. Barci2, X. Wang3, X. Zhou3, H. Jiao3, G. L. Donadio4, D. Garbin4, T. Witters4, S. Kundu4, H. Hody4, R. Delhougne4, G. S. Kar4 and M. Karner1 1Global TCAD Solutions (Austria) 2Huawei Technologies R&D Belgium N.V. (Belgium) 3HiSilicon Technologies (China) 4Imec (Belgium) |
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P16 |
Performance of Vertical Gate-All-Around Nanowire p-MOS Transistors Determined by Boron Depletion during Oxidation Chiara Rossi1, Alexander Burenkov1, Peter Pichler1, Eberhard Bär1, Paweł Piotr Michałowski2, Jonas Müller3 and Guilhem Larrieu3 1Fraunhofer Institute for Integrated Systems and Device Technology (IISB) (Germany) 2Łukasiewicz Research Network – Institute of Microelectronics and Photonics (Poland) 3LAAS-CNRS, Université de Toulouse (France) |
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P17 |
Polarization Switching Characteristics in AFE/FE Double-Layer Devices Mengqi Fan and Fei Liu, Xiaoyan Liu School of Integrated Circuits, Peking University (China) |
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P18 |
Scattering matrix-based low computational cost model for the device and circuit co-simulation of phosphorene tunnel field-effect transistors Kosuke Yamaguchi and Satofumi Souma Department of Electrical and Electronic Engineering, Kobe University (Japan) |
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P19 |
Sensitivity enhancement in OCD metrology by optimizing azimuth angle based on the RCWA simulation Hyunsuk Choi1, Kwangseok Lee1, Jiseong Doh1, Jaehoon Jeong1, Minseok Kim2, Yeonjeong Kim2, Jongchul Kim2, Hyung Keun Yoo2, Dae Sin Kim1 1Computationl Science and Engineering Team 2Foundry Metrology & Inspection Technology Team, Samsung Electronics Co., Ltd. (Republic of Korea) |
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P20 |
Strong quantization of current-carrying electron states in δ-layer systems Denis Mamaluy and Juan P. Mendez Sandia National Laboratories (USA) |
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P21 |
Non-local Transport Effects in Semiconductors Under Low-Field Conditions M.G. Ancona1,2 and S.J. Cooke2 1Department of Electrical and Computer Engineering, Florida State University (USA) 2Electronics Science and Technology Division, Naval Research Laboratory Washington (USA) |