Nanodevices and Interconnects
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14:30 – 14:50 |
Stacking devices in a vertical nanowire, a feasible option to implement smaller ICs E. Amat, A. del Moral, J. Bausells and F. Perez-Murano Institute of Microelectronics of Barcelona (IMB-CNM, CSIC) (Spain) |
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14:50 – 15:10 |
A comprehensive on-current variability Pelgrom-based model for FinFET, NWFET and NSFET transistors Julian G. Fernandez, Natalia Seoane, Enrique Comesaña and Antonio García-Loureiro CiTIUS, University of Santiago de Compostela (Spain) |
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15:10 – 15:30 |
Forked Contact and Dynamically-Doped Nanosheets to Enhance Si and 2D Materials Device at the limit of Scaling Aryan Afzalian, Zubair Ahmed and Julien Ryckaert Imec (Belgium) |
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15:30 – 15:50 |
On the Switching Limits of Top-Gated Carbon Nanotube Field-Effect Transistors A. Sanchez-Soares1, C. Gilardi2, Q. Lin2, T. Kelly1, S.-K. Su3, G. Fagas4, J.C. Greer5, G. Pitner6, E. Chen3 1EOLAS Designs, Grenagh, Co. (Republic of Ireland) 2Stanford University (USA) 3Corporate Research, TSMC (Taiwan) 4Tyndall National Institute, University College Cork (Ireland) 5University of Nottingham Ningbo China (China) 6Corporate Research, TSMC (USA) |
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15:50 – 16:10 |
28nm FDSOI MEOL Parasitic Capacitance Segmentation using Electrical Testing and Semiconductor Process Modeling B. Vianne1, B. Guillo-Lohan1, V. Quenette1, B. Legoix1 and B. Vincent2 1STMicroelectronics, Crolles, France 2Coventor, a Lam Research Company, Villebon sur Yvette, France |