III-V Devices
Wednesday 21
| 14:30 – 14:50 | 2D and 3D TCAD Simulation of III-V Channel FETs at the End of Scaling
P. Aguirre, M. Rau, and A. Schenk Integrated Systems Laboratory, ETH Zürich, Zürich, Switzerland
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| 14:50 – 15:10 | Investigation on Temperature Effects of Electrical Characteristics in GaAs DMG FinFET
Rajesh Saha, Brinda Bhowmick, and Srimanta Baishya Electronics and Communication Engineering Department, National Institute of Technology Silchar, Assam, India |
| 15:10 – 15:30 | On the Impact of Channel Compositional Variations on Total Threshold Voltage Variability in Nanoscale InGaAs MOSFETs
Nicolò Zagni1, Francesco Maria Puglisi1, Giovanni Verzellesi2, and Paolo Pavan1 1DIEF and 2DISMI, Università di Modena e Reggio Emilia, Via P. Vivarelli 10/1, 41125 Modena, Italy |
| 15:30 – 15:50 | Effects of Stress and Strain Distribution on Performance Analysis of GaN/InGaN/GaN Core/Shell/Shell Radial Nanowires for Solar Energy Harvesting
S. R. Routray, and T. R. Lenka Microelectronics & VLSI Design Group, Department of Electronics and Communication Engineering, National Institute of Technology Silchar, Assam, India-788010 |